(1) Field of the Invention
The invention relates to a flash memory device and, more particularly, to a method to form a flash memory device having sidewall coupling between the floating gate and source/drain plugs to improve programming efficiency.
(2) Description of the Prior Art
Flash memories are used in a large number of electronic applications. Flash memories can provide random access to stored data such as application programs. Flash memory cells can be written to and read from many times. In this way, flash memory is similar to static or dynamic RAM. However, as an additional advantage, flash memories can retain data during a loss of power supply. By comparison, RAM devices lose memory states if the power supply is removed.
A typical flash memory cell is a modified MOS transistor with a stacked gate. The stacked gate comprises a control gate and a floating gate. The control gate is used to turn the transistor OFF and ON and to thereby control current flow from the drain to the source. The floating gate is placed between the control gate and the device channel. Charge can be injected into or out of the floating gate where it becomes trapped due to the isolation material that surrounds the floating gate. The threshold voltage of the flash transistor cell varies with the charge-state of the floating gate. Binary data values are stored in each flash cell bas d on the floating gate charge-state.
The process of charging or discharging the floating gate is called erasing or programming. Erasing or programming the flash cell requires that electrons overcome an energy barrier, such as caused by an oxide layer, between the floating gate electrode and the charge source. The energy level of the electrons is raised above this energy barrier value by forcing a relatively large voltage across the barrier. For example, the flash cell may be erased by injecting electrons from the floating gate into the control state. The control gate is forced to a large positive voltage while the floating gate is capacitively coupled to a low voltage or to a negative voltage. Similarly, the drain, the source, or the channel region of the device may be used to source or to sink electrons during programming and erasing.
Applications of flash memory require that stored data be retained in the memory cells for extended periods. Therefore, the floating gate barrier energy must be large compared to the energy used to read the cell. However, creating a high, energy barrier further requires large programming and erasing voltages. It is also found in the prior art that the program and erase voltage is increased by inadequate capacitive coupling between the floating gate and the source or sink nodes, such as source, drain, or channel regions. That is, much of the voltage for programming or erasing is lost due to poor coupling to the floating gate. Therefore, larger voltage signals must used. These large voltages are generated using charge pump circuits or external supplies. Carefully designed devices or special processing must be used to handle these voltages on-chip. It is therefore a central object of the present invention to reduce the programming and erasing voltages for a flash device by improving the floating gate coupling coefficient.
Several prior art inventions relate to methods to form flash memory devices. U.S. Pat. No. 6,159,801 to Hsieh et al teaches a method to form a split-gate, flash transistor having improved coupling between source and floating gate. In one embodiment, the floating gate has a three-dimensional coupling to the source. The STI oxide bounding the source active area is recessed below the substrate surface such that the floating gate can overlap the source sidewalls. U.S. Pat. No. 6,153,494 to Hsieh et al discloses a method to form a stacked gate, flash cell having improved word line and floating gate coupling. The STI oxide is formed protruding above the surface of the substrate. The floating gates formed between the STI regions have a three-dimensional topology such that the coupling area between the floating gates and the word lines is increased. U.S. Pat. No. 5,998,263 to Sekariapuram et al describes an EEPROM cell having a vertical channel. U.S. Pat. No. 6,200,856 to Chen teaches a flash cell having a self-aligned, stacked gate.